Applying Machine Learning in VLSI Chip Design

ASIC Design | 17 April 2018

This blog post contains a collection of research papers, books, labs, conferences and additional resources that solve problems related to Advanced VLSI (Chip) Logic Design, Physical Design, Synthesis and Verification using Machine Learning and Deep Learning. Feel free to add a paper or an article related to this domain by commenting below so that I will include it here 😊

CAEML Research Topics

  • Modular Machine Learning for Behavioral Modeling of Microelectronic Circuits and Systems - [link]
  • Behavioral Model Development for High-Speed Links - [link]
  • Design Rule Checking with Deep Networks - [link]
  • Optimization of Power Delivery Networks for Maximizing Signal Integrity - [link]
  • Intellectual Property Reuse Through Machine Learning - [link]
  • Models to Enable System-level Electrostatic Discharge Analysis - [link]
  • Applying Machine Learning to Back End IC Design - [link]
  • Models to Enable System-level Electrostatic Discharge Analysis - [link]
  • Causal Inference for Early Detection of Hardware Failure - [link]
  • NL2PPA: Netlist‐to‐PPA Prediction Using Machine Learning - [link]
  • Fast, Accurate PPA Model‐Extraction - [link]
  • Design Space Exploration Using DNN - [link]
  • High-Speed Bus Physical Design Analysis through Machine Learning - [link]


If you wish to learn how to build a chip, I have collected these resources for you!

In case if you found something useful to add to this article or you found a bug in the code or would like to improve some points mentioned, feel free to write it down in the comments. Hope you found something useful here.