In this blog post, we will learn the basic concepts involved in Static Timing Analysis and understand why it is highly preferred in practice to meet timing.
When designing a chip, performance is the number one concern for chip designers. The chip needs to meet timing to work properly else user experience suffers. To verify whether a design meets timing, there are different techniques such as Timing Simulation, Static Timing Analysis (STA) and Dynamic Timing Analysis (DTA).
1 2 3 4 What is Static Timing Analysis (STA)? Why STA is used? What are timing paths? What are the different types of delays?
Static Timing Analysis
According to Wikipedia, Static timing analysis (STA) is a simulation method of computing the expected timing of a digital circuit without requiring a simulation of the full circuit.
In other words, STA is the method of summing up cell delays and net delays in a design (which equals path delays) and comparing the path delays to the constraints (timing specifications).
STA is done at many stages in a typical ASIC design flow (Figure 1). Performing STA before detail routing only provides the approximations based on different factors. But the real picture of STA is obtained only after detail routing the entire design in the layout phase (physical design). This is because, only after detail routing the entire design, parasitics are extracted (Resistances and Capacitances) based on detailed routes which is an important input to perform STA.
As you might know, a smartphone or a laptop or a tablet runs by the clock frequency (which is given by the specifications). Due to this predefined clock frequency, it is necessary for the design to meet this frequency under different external environmental conditions which includes Process, Voltage and Temperature (PVT). Thus, the purpose of STA is to check if the design can operate at the desired speed (frequency) under different external environmental conditions.
Characteristics of STA
- STA is a complete and exhaustive technique of verifying the timing of a chip.
- STA is fast and accurate measurement of circuit timing.
- STA does not check for logical functionality in the design.
- STA uses simplified timing models to check for violations in the design.
- STA is all about analyzing the cell delays and net delays over millions of paths in a design and fixing if any violation arises in those paths by comparing with the timing constraints.
- STA analyzes entire design once and the required timing checks are carried out for all possible paths and scenarios of the design.
- STA is the mainstay of design over the last few decades.
- STA = Delay calculation + Timing Checks
- Types of timing checks performed in STA are
- Setup check
- Hold check
- Recovery check
- Removal check
- Data-to-Data user-specified timing check
- Clock-gating check
- Minimum period check
- Minimum pulse width check
- Design rule checks (min/max transition time, capacitance, fanout)
Did you know: The word Static in STA is due to the fact that it does not depend on the data values being applied at the inputs and the whole timing analysis is based on simplified timing models and delays.
When a gate-level netlist is available, STA is done based on
- Interconnect modelling - ideal, wireload model, global routes (approximate RC values), detail routes (accurate RCs).
- Clock modelling - ideal clocks (zero delay) or propagated clocks (real delays).
- Crosstalk & Noise - Coupling between signals (metal traces).
For a typical design which includes 10-100 million gates, there exists huge number of timing paths. These timing paths are defined by timing arcs which we discussed in the previous tutorial.
There are two types of timing arcs in a timing path.
- Cell timing arc - Timing arc between an input pin and the output pin of a cell.
- Net timing arc - Timing arc of a net (wire) that is between a driver (output pin) and a load (input pin).
The basic measures of the above imaginary timing arcs are
- Delay - Provided in the cell library (for cell) and SPEF (for net).
- Unateness - Provided in the cell library (for cell) and always positive unate (for net).
- Transition time - Provided as slew thresholds in the cell library (for cell).
A timing path has a start point and an end point.
- Start point - All input ports/pins or clock ports/pins of sequential cells are considered as start points.
- End points - All output ports/pins or D pin of sequential cells are considered as end points.
Based on the above mentioned start point and end point, there are four types of timing paths (Figure 2) based on direction.
- Input to Register - Start point is an input pin/port and end point is the D pin/port of a register (flipflop). It might include both combinational and sequential cells.
- Register to Register - Start point is the CLK pin/port of a register (flipflop) and end point is the D pin/port of next register (flipflop). Also, this type of path might include combinational and sequential cells.
- Register to Output - Start point is the CLK pin/port of a register (flipflop) and end point is an output pin/port. Both sequential and combinational cells are included here.
- Input to Output - Start point is an input pin/port and end point is an output pin/port. It includes combinational cells only.
In addition to the above timing paths, based on signal type, there are two additional types of timing path categorization in a design.
- Clock path - The timing path which is fully traversed by clock signals is called as Clock path. In a clock path, there could only be clock inverters or clock buffers. Additionally, to save power, there could be presence of clock gating cells in this clock path (ex: AND gate). Such paths are called as “Gated clock paths”. Clock paths are further categorized into two types.
- Launch path - The timing path which is traversed by the clock signal from source pin to launch register (flipflop) CLK pin (FF1 in Figure 2).
- Capture path - The timing path which is traversed by the clock signal from source pin to capture register (flipflop) CLK pin (FF2 in Figure 2).
- Data path - The timing path which is fully traversed by data signals is called as Data path. In a data path, there could be combinational cells, data buffers etc.,
In the real world, delays are what makes STA interesting! Due to delays, there arises timing violations and the job of a chip design engineer is to analyze and understand these delays, and fix the timing violations. There are two types of delays in STA.
1. Cell delay
CMOS transistors inside a standard cell takes finite amount of time to switch from one logic state to another. This time taken is called as the cell delay or the propagation delay of a cell which is typically specified in the cell timing library (.lib).
The propagation delay of a standard cell depends on three factors (Figure 4).
- Input Slew - The transition time at the input i.e. the time it takes for an input pin (input capacitance) to switch between logic states (low-high or high-low).
- Output Capacitance - The capacitance that needs to get charged/discharged at the output of a cell driving single or multiple loads. This capacitance introduces a finite amount of delay.
- Intrinsic Delay - The internal delay of a cell when a signal with zero transition time is applied to the input pin and no output load is present.
2. Net delay
Interconnect delay or net delay is due to the physical wire (metal traces having resistances and capacitances) of a logical net (i.e. between a driver and load/loads). All net timing arcs are positive unate. This is because there can be either rise-rise transition from driver to load or fall-fall transition from driver to load.
Net delay is calculated using two methods depending on the design phase.
- Wire-load models (approximate - used in logic design) - Based on statistics and poisson distribution to calculate the resistance and capacitance values of the nets based on length, fanout and area.
- Actual physical layout estimate (accurate - used in physical design) - Uses backannotation i.e. the process of extracting the resistances and capacitances after detail routing all the nets in a design (also called as parasitic extraction). There are three different file formats for representing parasitics in a design for timing analysis.
- Detailed Standard Parasitic Format (DSPF)
- Reduced Standard Parasitic Format (RSPF)
- Standard Parasitic Exchange Format (SPEF)
Did you know: SPEF is the industry standard file format of choice to represent parasitic values (resistances and capacitances) of a design.
Min and Max Timing Paths
Apart from the functionality based timing paths, there exist two types of timing paths based on path delay. Path delay = Cell delay + Net delay. As there are multiple ways for the logic to propagate from one start point to an end point (Figure 5), the maximum and minimum timing paths can be calculated easily based on cell delay and net delay.
- Min path: The path between two points with shortest delay.
- Max path: The path between two points with largest delay.
In the next post, we will understand various concepts involved in STA such as setup time, hold time, max delay, min delay etc.,
- Static Timing Analysis for Nanometer Designs: A Practical Approach, Jayaram Bhasker and Rakesh Chadha.
- Digital Integrated Circuits: A Design Perspective, Jan Rabaey.
In case if you found something useful to add to this article or you found a bug in the code or would like to improve some points mentioned, feel free to write it down in the comments. Hope you found something useful here.